1. Field of the Invention
The present invention relates to an improved structure for a probe card used in a probing test equipment, and more particularly to a multi-test probe card with a ground shield structure to reduce the ground noise coupling effect between adjacent chips on a wafer during testing. The ground shield structure includes a plurality of ground paths arranged across the central window of the probe card and interconnected to the ground layer or a ground shield layer in the probe card to form a ground shield to each adjacent semiconductor chip from each other.
2. Description of the Prior Art
In the manufacture of integrated circuits, it is necessary to test the electrical characteristics of the chips on a wafer by means of a probing test equipment (known as prober). Typically, the probing test equipment includes a probe car(d to perform the test under control of a tester. The probe card is mounted with a plurality of testing pins. Each of the testing pins is in the form as a fine need with an L-shaped structure. The testing pins are disposed so that its front end may project downwardly toward the corresponding contact pad on a semiconductor chip to be tested.
An example of a prior art probe card structure for probing test equipment is disclosed in U.S. Pat. No. 5,134,365 issued Jul. 28, 1992, issued to Okubo et al entitled "probe card in which contact pressure and relative position of each probe end are correctly maintained." This first reference probe card discloses a probe card which includes a resin layer of an elastic, insulative characteristic to fill the central open area or window of the supporter assembled into the probe card. The resin layer makes the probe front ends resiliently held in position so that a deviation from proper respective dispositions by overdrive becomes avoidable. In addition, this prior art U.S. patent discloses an additional devices to enhance the convenience in determining the alignment between the probe front ends and the chip ends, and also in obtaining accurate measurements of a semiconductor chip under test. It is noted that this prior art U.S. patent is adapted to be used in single-test operation. Besides, this prior art patent does not disclose ground noise reducing design.
Another example of the prior art probe card structure is disclosed in U.S. Pat. No. 5,412,329 issued May 2, 1995, issued to lino et al entitled "probe card" discloses a probe card composed of a supporting plate and a flexible printed circuit board which includes a flexible film base material supported by the supporting plate. When the contact point is brought into contact with the pad formed on the semiconductor chip, the cushioning medium undergoes an elastic deformation, so that the contact between the contact points and the pads is improved. Also, this prior art U.S. patent does not disclose any approach for reducing ground noise during test.
FIG. 1 is a schematic block diagram showing a general structure of a prior art probing test equipment. As shown in the drawing, the prober mainly includes a tester 11, a test head 12, and a probe card 13. A wafer 14 to be tested is located on a chuck 15 which is arranged to face the probe card 13 in space. FIG. 2 is an exploded view showing the arrangement of the conventional probe card 13, the wafer 14, and the chuck 15 of FIG. 1. A number of semiconductor chips are formed on the wafer 13. Typically, the chuck 15 includes a vacuum suction device (not shown in the drawing) for retaining the wafer 14 on the chuck table.
The tester 11 serves as a controller for controlling the test operation of the prober, which is capable of transmitting test signals to the test head 12 and receiving echo signals from the wafer 14 via the test head 12. The test head 12 is equipped with a plurality of downward contact pins 121, and each of the contact pins is electrically connected to the tester 11. The test head serves as an interface for the tester 11 and the probe card 13.
The probe card 13 is located right under the test head 12. A number of contact points 133 are arranged on the surface of the probe card 13, so that each of the contact pins 121 of the test head 12 may electrically contact with corresponding contact point arranged on the probe card 13 during test.
Further, the conventional probe card 13 is formed with a central open area or window 131 at the central portion thereof, so that a selected chip to be tested on the wafer 14 may be observed through the window 131 by means of an optical position sensor, such as a CCD camera (not shown).
The probe card 13 is fitted with a number of downward testing pins 132 which may be arranged in the form of a regular lattice or circular form, dependent on the contact pad arrangement on the semiconductor chip to be tested. Practically, in large-scale integrated circuit, such as memory device or other device, the contact pads are arranged in the central region of the chip as well as the peripheral regions. The testing pins are disposed so that its front end may project downwardly toward a semiconductor chip. Typically, the testing pins 132 are made of tungsten or Au--Cu alloy. The number of the testing pins 132 is equal to the contact pads on the semiconductor chip both in number and in arrangement.
Each testing pin 132 of the probe card is electrically connected to the corresponding contact point 133 by a wiring layout pattern formed on the probe card, so that the test signal from the tester 11 may transmit to the individual testing pin 132 of the probe card 13 via the test head 12 during test.
FIG. 3 is an exploded view showing an improved probe card structure in accordance with another prior art prober. FIG. 4 illustrates the top plan view of the prior art probe card 20 of FIG. 3. This type of probe card is known as multi-test probe card because it is particularly adapted to be used for multi-test operation. For explanation, the same reference numbers used in the previous drawing will be used to refer to the same or like parts.
As shown in FIGS. 3 and 4. it is noted that a number of contact points 203 are also arranged on the probe card 20 for contacting with the contact pins of the test head as described above. However, the probe card 20 is formed with a rectangular window 201 instead of the square window shown in FIG. 2. The dimensions of the rectangular window 201 is designed to cover multiple semiconductor chips on the wafer 14 to perform multi-test function, known as parallel testing. In this case, the testing pins 202 of the probe card 20 are divided into four groups. In other words, four chips on the wafer 14 may be observed through the rectangular window 201 by means of an optical position sensor (not shown). So, the probe card 20 can test four chips at one test time in this case.
FIG.5 is a cross-sectional view of the conventional multi-test probe card 20, taken along line 1--1 of FIG. 4. The probe card 20 is composed of a multi-layer printed circuit board with a central window 201 formed at the central portion of the circuit board and a plurality of testing pins 202. The circuit board includes a power source layer 205, such as Vcc layer, and a ground layer 206 therein. Typically, an insulative film 207 is further formed on the ground layer 206, so that a number of contact points 203 may be arranged on the circuit board. Each contact point 203 arranged on the circuit board is electrically coupled to the corresponding testing pin 202 attached to the bottom surface of the circuit board via a conductive path 204 by well known printed circuit layout technique. Each of the testing pins 202 are further fixed and held by means of an insulative resin or rubber block 208 in position.
With reference to FIG. 4 and FIG. 5, the ground layer 206 which is mounted in the printed circuit board of the probe card 20 forms a ground path structure to surround the central window 201 of the probe card 20. In practice, the ground path is electrically connected to a number of specific testing pins 202, as particularly shown in FIG. 4.
Theoretically speaking, mutual inductance results when an electric current I flows through a closed circuit loop. The mutual inductance will produce a magnetic flux .PHI. which is proportional to the amount of the current I. The constant of proportionality is called the inductance L. Therefore, we may write .PHI.=LI. The amount of the inductance value depends on the geometry of the circuit loop layout and the magnetic properties of the medium containing the field. When an electric current flowing through a first circuit loop produces a mutual flux in a second circuit loop, there will be a mutual inductance M12 occurred between the first circuit loop and the second circuit loop. The mutual inductance M12 is defined as .PHI.12/I1. The symbol .PHI.12 represents the flux in the second circuit loop caused by the current I1 in the first circuit loop. Similarly, it can also be derived a mutual inductance between a shield and a center conductor, which may be referred as a shield inductance. By decreasing the shield inductance, the center conductance inductance may be decreased.
FIG. 6 is an equivalent schematic circuit diagram illustrating the ground noise created between two adjacent circuit loops. Ideally, the first currents I11 flowing through the first loop is equal to the second current I22 flowing through the second loop. However, in case the first loop resister R11 is not equal to the second loop resister R22, the first inductance L11 will be not equal to the second inductance L22. It is be better understood from the following calculation: EQU XL11=2.pi.fL11 EQU XL22=2.pi.ff22 EQU X11=R11+2.pi.fL11 EQU X22=R22+2.pi.fL22 EQU V11=I11(R11+2.pi.fL11) EQU V22=I22(R22+2.pi.fL22)
The XL11 represents the inductive reactance offered by the inductance L11 of the first loop. The X11 represents the combined impedance of the resistor R11 and the inductive reactance XL11 of the first loop. The V11 is defined as the voltage drop developed across the combined impedance X11 by the first loop current I11 through the resistor R11 and the inductive reactance XL11.
Similarly, the XL22 represents the inductive reactance offered by the inductance L22 of the second loop. The X22 represents the combined impedance of the resistor R22 and the inductive reactance XL22 of the second loop. The V22 is defined as the voltage drop developed across the combined impedance X22 by the second loop current I22 through the resistor R22 and the inductive reactance XL22.
It is noted that a noise will be created by the potential existed between the V22 and the V11.
In performing the probing test for semiconductor chips by using a probing test equipment, ground noise is coming from the ground wire inductance and resistance existing on the probe card. During parallel testing by using the prior art multi-test probe card as shown in FIG. 3, the ground noise from adjacent devices are injected to the next device and thereby creating a complex ground noise coupling effect. Although the ground paths in printed circuit board of the probe card have been sandwiched very carefully, it is hard to isolate each device individually. It is deemed that the conventional probe cards cannot execute a reliable probing test.
During parallel testing, ground noise from adjacent devices are also injected to the next device, and thereby creating a more serious ground noise coupling effect. In practical experience, when the number of testing pins is increased to more than 300 to 600 pins, and the semiconductor chips to be tested are more than 10, it will have an undesired ground noise coupling effect during test. This ground noise is mainly due to the inductance and resistance of the grounding wires. The ground noise occurred will seriously effect the reliability of the probing test.